/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

/*****************************************************************************/
/* Version: GNU Compiler Collection                                          */
/*****************************************************************************/

    MODULE  ?cstartup

        ;; Forward declaration of sections.
        SECTION CSTACK:DATA:NOROOT(3)

        SECTION .intvec:CODE:ROOT(2)

        EXTERN  main
        EXTERN  SystemInit
        EXTERN  init_data_bss
        PUBLIC  __vector_table
        PUBLIC  __vector_table_0x1c
        PUBLIC  __Vectors
        PUBLIC  __Vectors_End
        PUBLIC  __Vectors_Size

        DATA

__vector_table
        DCD   sfe(CSTACK)
        DCD   Reset_Handler                         ; Reset Handler
        DCD   NMI_Handler                        ; Non Maskable Interrupt
        DCD   HardFault_Handler                  ; Cortex-M0 SV Hard Fault Interrupt
        DCD   0
        DCD   0
        DCD   0
__vector_table_0x1c
        DCD   0
        DCD   0
        DCD   0
        DCD   0
        DCD   SVC_Handler                        ; Cortex-M0 SV Call Interrupt
        DCD   0
        DCD   0
        DCD   PendSV_Handler                     ; Cortex-M0 Pend SV Interrupt
        DCD   SysTick_Handler                    ; Cortex-M0 System Tick Interrupt


        DCD   DMA01_Handler                   /*  0 (040H) DMA channel 0,1 transfer complete*/
        DCD   DMA23_Handler                   /*  1 (044H) DMA channel 2,3 transfer complete*/
        DCD   DMA_Error_Handler               /*  2 (048H) DMA error interrupt channels 0-3*/
        DCD   FHU_Handler                     /*  3 (04CH) FHU Interrupt, ERM single bit error correction*/
        DCD   RTC_Alarm_Handler               /*  4 (050H) RTC alarm interrupt*/
        DCD   RTC_Seconds_Handler             /*  5 (054H) RTC seconds interrupt*/
        DCD   LPTMR_Handler                   /*  6 (058H) LPTIMER interrupt request*/
        DCD   PORT_Handler                    /*  7 (05CH) Port ABCDE pin detect interrupt */
        DCD   CAN_ORed_Handler                /*  8 (060H) CAN OR'ed [BusOff\BusOffDone\TransWarning\ReceiveWarning\..... ] */
        DCD   CAN_ORed_0_31_MB_Handler        /*  9 (064H) CAN OR'ed Message buffer (0-31) */
        DCD   CAN_ORed_32_63_MB_Handler       /* 10 (068H) CAN OR'ed Message buffer (32-63) */
        DCD   MFT0_Ch0_Ch7_Handler            /* 11 (06CH) MFT0 Channel 0 to 7 interrupt */
        DCD   MFT0_Fault_Handler              /* 12 (070H) MFT0 Fault interrupt */
        DCD   MFT0_Ovf_Reload_Handler         /* 13 (074H) MFT0 Counter overflow and Reload interrupt */
        DCD   MFT1_Ch0_Ch7_Handler            /* 14 (078H) MFT1 Channel 0 to 7 interrupt */
        DCD   MFT1_Fault_Handler              /* 15 (07CH) MFT1 Fault interrupt */
        DCD   MFT1_Ovf_Reload_Handler         /* 16 (080H) MFT1 Counter overflow and Reload interrupt */
        DCD   FTFC_Handler                    /* 17 (084H) FTFC Command done,read collision,err response interrupt */
        DCD   PDB_Handler                     /* 18 (088H) PDB interrupt */
        DCD   LPIT_Handler                    /* 19 (08CH) LPIT interrupt */
        DCD   CMU_Handler                     /* 20 (090H) CMU PLL,SOSC interrupt */
        DCD   WDOG_Handler                    /* 21 (094H) Interrupt request out before wdg reset out */
        DCD   RCM_Handler                     /* 22 (098H) RCM Asynchronous Interrupt, Reset interrutpt */
        DCD   I2C_Handler                     /* 23 (09CH) I2C Interrupt */
        DCD   SPI0_Handler                    /* 24 (0A0H) SPI0 Interrupt */
        DCD   SPI1_Handler                    /* 25 (0A4H) SPI1 Interrupt */
        DCD   ADC_Handler                     /* 26 (0A8H) ADC interrupt request. */
        DCD   CMP_Handler                     /* 27 (0ACH) CMP interrupt request */
        DCD   I2S_SLV_MST_Handler             /* 28 (0B0H) I2S Slave and Master interrupt */
        DCD   UART0_RxTx_Handler              /* 29 (0B4H) UART0 Transmit / Receive Interrupt */
        DCD   UART1_RxTx_Handler              /* 30 (0B8H) UART1 Transmit / Receive  Interrupt */
        DCD   UART2_RxTx_Handler              /* 31 (0BCH) UART2 Transmit / Receive  Interrupt */
__Vectors_End

        SECTION FlashConfig:CODE
__FlashConfig
        DCD 0xD28FC027
        DCD 0xDC4DD3A0
        DCD 0x00000000
        DCD 0xFFFF0000
        DCD 0xFFFFFFBF
        DCD 0xFFFFFFFF
        DCD 0xBEE688FE
        DCD 0x8E5BA230
__FlashConfig_End

__Vectors       EQU   __vector_table
__Vectors_Size  EQU   __Vectors_End - __Vectors


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
        THUMB

        PUBWEAK Reset_Handler
        SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
        CPSID   I               ; Mask interrupts
        ;; Init the rest of the registers
        LDR     R1,=0
        LDR     R2,=0
        LDR     R3,=0
        LDR     R4,=0
        LDR     R5,=0
        LDR     R6,=0
        LDR     R7,=0
        MOV     R8,R7
        MOV     R9,R7
        MOV     R10,R7
        MOV     R11,R7
        MOV     R12,R7

#ifdef START_FROM_FLASH
        IMPORT __RAM_START, __RAM_END
        ;; INIT ECC RAM

        LDR R1, =__RAM_START
        LDR R2, =__RAM_END

        SUBS    R2, R2, R1
        SUBS    R2, #1
        BLE .LC5

        MOVS    R0, #0
        MOVS    R3, #4
    .LC4:
        STR R0, [R1]
        ADD	R1, R1, R3
        SUBS R2, #4
        BGE .LC4
    .LC5:
#endif
        ;; Initialize the stack pointer
        LDR     R0, =sfe(CSTACK)
        MOV     R13,R0

#ifndef __NO_SYSTEM_INIT
        ;; Call the CMSIS system init routine
        LDR     R0, =SystemInit
        BLX     R0
#endif

        ;; Init .data and .bss sections
        LDR     R0, =init_data_bss
        BLX     R0
        CPSIE   I               ; Unmask interrupts
        BL      main
JumpToSelf
        B   JumpToSelf

        PUBWEAK NMI_Handler
        SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
        B .

        PUBWEAK HardFault_Handler
        SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
        B .


        PUBWEAK SVC_Handler
        SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
        B .

        PUBWEAK PendSV_Handler
        SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
        B .

        PUBWEAK SysTick_Handler
        SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
        B .

        PUBWEAK     DMA01_Handler
        PUBWEAK     DMA23_Handler
        PUBWEAK     DMA_Error_Handler
        PUBWEAK     FHU_Handler
        PUBWEAK     RTC_Alarm_Handler
        PUBWEAK     RTC_Seconds_Handler
        PUBWEAK     LPTMR_Handler
        PUBWEAK     PORT_Handler
        PUBWEAK     CAN_ORed_Handler
        PUBWEAK     CAN_ORed_0_31_MB_Handler
        PUBWEAK     CAN_ORed_32_63_MB_Handler
        PUBWEAK     MFT0_Ch0_Ch7_Handler
        PUBWEAK     MFT0_Fault_Handler
        PUBWEAK     MFT0_Ovf_Reload_Handler
        PUBWEAK     MFT1_Ch0_Ch7_Handler
        PUBWEAK     MFT1_Fault_Handler
        PUBWEAK     MFT1_Ovf_Reload_Handler
        PUBWEAK     FTFC_Handler
        PUBWEAK     PDB_Handler
        PUBWEAK     LPIT_Handler
        PUBWEAK     CMU_Handler
        PUBWEAK     WDOG_Handler
        PUBWEAK     RCM_Handler
        PUBWEAK     I2C_Handler
        PUBWEAK     SPI0_Handler
        PUBWEAK     SPI1_Handler
        PUBWEAK     ADC_Handler
        PUBWEAK     CMP_Handler
        PUBWEAK     I2S_SLV_MST_Handler
        PUBWEAK     UART0_RxTx_Handler
        PUBWEAK     UART1_RxTx_Handler
        PUBWEAK     UART2_RxTx_Handler
        PUBWEAK 	DefaultISR
        SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
HardFault_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
DMA01_Handler
DMA23_Handler
DMA_Error_Handler
FHU_Handler
RTC_Alarm_Handler
RTC_Seconds_Handler
LPTMR_Handler
PORT_Handler
CAN_ORed_Handler
CAN_ORed_0_31_MB_Handler
CAN_ORed_32_63_MB_Handler
MFT0_Ch0_Ch7_Handler
MFT0_Fault_Handler
MFT0_Ovf_Reload_Handler
MFT1_Ch0_Ch7_Handler
MFT1_Fault_Handler
MFT1_Ovf_Reload_Handler
FTFC_Handler
PDB_Handler
LPIT_Handler
CMU_Handler
WDOG_Handler
RCM_Handler
I2C_Handler
SPI0_Handler
SPI1_Handler
ADC_Handler
CMP_Handler
I2S_SLV_MST_Handler
UART0_RxTx_Handler
UART1_RxTx_Handler
UART2_RxTx_Handler
DefaultISR

        END
