/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _PCC0_REG_H_
#define _PCC0_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the PCC0 Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* CMP Bit Fields */
#define PCC0_CMP_SRC_MASK        (0x10000u)
#define PCC0_CMP_SRC_SHIFT       (16u)
#define PCC0_CMP_SRC_WIDTH       (1u)
#define PCC0_CMP_CKEN_MASK       (0x10u)
#define PCC0_CMP_CKEN_SHIFT      (4u)
#define PCC0_CMP_CKEN_WIDTH      (1u)
#define PCC0_CMP_SWR_MASK        (0x01u)
#define PCC0_CMP_SWR_SHIFT       (0u)
#define PCC0_CMP_SWR_WIDTH       (1u)

/* PORTA Bit Fields */
#define PCC0_PORTA_CKEN_MASK     (0x10u)
#define PCC0_PORTA_CKEN_SHIFT    (4u)
#define PCC0_PORTA_CKEN_WIDTH    (1u)
#define PCC0_PORTA_SWR_MASK      (0x01u)
#define PCC0_PORTA_SWR_SHIFT     (0u)
#define PCC0_PORTA_SWR_WIDTH     (1u)

/* PORTB Bit Fields */
#define PCC0_PORTB_CKEN_MASK     (0x10u)
#define PCC0_PORTB_CKEN_SHIFT    (4u)
#define PCC0_PORTB_CKEN_WIDTH    (1u)
#define PCC0_PORTB_SWR_MASK      (0x01u)
#define PCC0_PORTB_SWR_SHIFT     (0u)
#define PCC0_PORTB_SWR_WIDTH     (1u)

/* PORTC Bit Fields */
#define PCC0_PORTC_CKEN_MASK     (0x10u)
#define PCC0_PORTC_CKEN_SHIFT    (4u)
#define PCC0_PORTC_CKEN_WIDTH    (1u)
#define PCC0_PORTC_SWR_MASK      (0x01u)
#define PCC0_PORTC_SWR_SHIFT     (0u)
#define PCC0_PORTC_SWR_WIDTH     (1u)

/* PORTD Bit Fields */
#define PCC0_PORTD_CKEN_MASK     (0x10u)
#define PCC0_PORTD_CKEN_SHIFT    (4u)
#define PCC0_PORTD_CKEN_WIDTH    (1u)
#define PCC0_PORTD_SWR_MASK      (0x01u)
#define PCC0_PORTD_SWR_SHIFT     (0u)
#define PCC0_PORTD_SWR_WIDTH     (1u)

/* PORTE Bit Fields */
#define PCC0_PORTE_CKEN_MASK     (0x10u)
#define PCC0_PORTE_CKEN_SHIFT    (4u)
#define PCC0_PORTE_CKEN_WIDTH    (1u)
#define PCC0_PORTE_SWR_MASK      (0x01u)
#define PCC0_PORTE_SWR_SHIFT     (0u)
#define PCC0_PORTE_SWR_WIDTH     (1u)

/* LPTMR Bit Fields */
#define PCC0_LPTMR_SRC_MASK      (0x70000u)
#define PCC0_LPTMR_SRC_SHIFT     (16u)
#define PCC0_LPTMR_SRC_WIDTH     (3u)
#define PCC0_LPTMR_DIV_MASK      (0x700u)
#define PCC0_LPTMR_DIV_SHIFT     (8u)
#define PCC0_LPTMR_DIV_WIDTH     (3u)
#define PCC0_LPTMR_CKEN_MASK     (0x10u)
#define PCC0_LPTMR_CKEN_SHIFT    (4u)
#define PCC0_LPTMR_CKEN_WIDTH    (1u)
#define PCC0_LPTMR_SWR_MASK      (0x01u)
#define PCC0_LPTMR_SWR_SHIFT     (0u)
#define PCC0_LPTMR_SWR_WIDTH     (1u)

/* LPIT Bit Fields */
#define PCC0_LPIT_SRC_MASK       (0x30000u)
#define PCC0_LPIT_SRC_SHIFT      (16u)
#define PCC0_LPIT_SRC_WIDTH      (2u)
#define PCC0_LPIT_CKEN_MASK      (0x10u)
#define PCC0_LPIT_CKEN_SHIFT     (4u)
#define PCC0_LPIT_CKEN_WIDTH     (1u)
#define PCC0_LPIT_SWR_MASK       (0x01u)
#define PCC0_LPIT_SWR_SHIFT      (0u)
#define PCC0_LPIT_SWR_WIDTH      (1u)

/* RTC_CNT Bit Fields */
#define PCC0_RTC_CNT_SRC_MASK    (0x30000u)
#define PCC0_RTC_CNT_SRC_SHIFT   (16u)
#define PCC0_RTC_CNT_SRC_WIDTH   (2u)
#define PCC0_RTC_CNT_CKEN_MASK   (0x10u)
#define PCC0_RTC_CNT_CKEN_SHIFT  (4u)
#define PCC0_RTC_CNT_CKEN_WIDTH  (1u)

/* WDG Bit Fields */
#define PCC0_WDG_SWR_MASK        (0x01u)
#define PCC0_WDG_SWR_SHIFT       (0u)
#define PCC0_WDG_SWR_WIDTH       (1u)

/* PORTA_FLT Bit Fields */
#define PCC0_PORTA_FLT_SRC_MASK  (0x10000u)
#define PCC0_PORTA_FLT_SRC_SHIFT (16u)
#define PCC0_PORTA_FLT_SRC_WIDTH (1u)

/* PORTB_FLT Bit Fields */
#define PCC0_PORTB_FLT_SRC_MASK  (0x10000u)
#define PCC0_PORTB_FLT_SRC_SHIFT (16u)
#define PCC0_PORTB_FLT_SRC_WIDTH (1u)

/* PORTC_FLT Bit Fields */
#define PCC0_PORTC_FLT_SRC_MASK  (0x10000u)
#define PCC0_PORTC_FLT_SRC_SHIFT (16u)
#define PCC0_PORTC_FLT_SRC_WIDTH (1u)

/* PORTD_FLT Bit Fields */
#define PCC0_PORTD_FLT_SRC_MASK  (0x10000u)
#define PCC0_PORTD_FLT_SRC_SHIFT (16u)
#define PCC0_PORTD_FLT_SRC_WIDTH (1u)

/* PORTE_FLT Bit Fields */
#define PCC0_PORTE_FLT_SRC_MASK  (0x10000u)
#define PCC0_PORTE_FLT_SRC_SHIFT (16u)
#define PCC0_PORTE_FLT_SRC_WIDTH (1u)

/* LPO32 Bit Fields */
#define PCC0_LPO32_CKEN_MASK     (0x10u)
#define PCC0_LPO32_CKEN_SHIFT    (4u)
#define PCC0_LPO32_CKEN_WIDTH    (1u)

/* LPO1 Bit Fields */
#define PCC0_LPO1_CKEN_MASK      (0x10u)
#define PCC0_LPO1_CKEN_SHIFT     (4u)
#define PCC0_LPO1_CKEN_WIDTH     (1u)

/* LOCK Bit Fields */
#define PCC0_LOCK_LOCK_MASK      (0x01u)
#define PCC0_LOCK_LOCK_SHIFT     (0u)
#define PCC0_LOCK_LOCK_WIDTH     (1u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of PCC0 registers
 */
typedef struct _Pcc0RegType_
{
    uint32_t                RESERVED0[1];  /*!< Reserved register, offset: 0x0 */
    volatile uint32_t       CMP;           /*!< CMP clock and software reset control register, offset: 0x4 */
    volatile uint32_t       PORTA;         /*!< PORTA clock and software reset control register, offset: 0x8 */
    volatile uint32_t       PORTB;         /*!< PORTB clock and software reset control register, offset: 0xC */
    volatile uint32_t       PORTC;         /*!< PORTC clock and software reset control register, offset: 0x10 */
    volatile uint32_t       PORTD;         /*!< PORTD clock and software reset control register, offset: 0x14 */
    volatile uint32_t       PORTE;         /*!< PORTE clock and software reset control register, offset: 0x18 */
    volatile uint32_t       LPTMR;         /*!< LPTMR clock and software reset control register, offset: 0x1C */
    volatile uint32_t       LPIT;          /*!< LPIT clock and software reset control register, offset: 0x20 */
    uint32_t                RESERVED1[1];  /*!< Reserved register, offset: 0x24 */
    volatile uint32_t       RTC_CNT;       /*!< RTC clock and software reset control register, offset: 0x28 */
    volatile uint32_t       WDG;           /*!< WDG clock and software reset control register, offset: 0x2C */
    volatile uint32_t       PORTA_FLT;     /*!< PORTA digital filter clock and software reset control register, offset: 0x30 */
    volatile uint32_t       PORTB_FLT;     /*!< PORTB digital filter clock and software reset control register, offset: 0x34 */
    volatile uint32_t       PORTC_FLT;     /*!< PORTC digital filter clock and software reset control register, offset: 0x38 */
    volatile uint32_t       PORTD_FLT;     /*!< PORTD digital filter clock and software reset control register, offset: 0x3C */
    volatile uint32_t       PORTE_FLT;     /*!< PORTE digital filter clock and software reset control register, offset: 0x40 */
    volatile uint32_t       LPO32;         /*!< LPO32 clock and software reset control register, offset: 0x44 */
    volatile uint32_t       LPO1;          /*!< LPO1 clock and software reset control register, offset: 0x48 */
    uint32_t                RESERVED2[13]; /*!< Reserved register, offset: 0x4C */
    volatile uint32_t       KEY;           /*!< PCC module unlock/lock control, offset: 0x80 */
    const volatile uint32_t LOCK;          /*!< PCC module unlock/lock status, offset: 0x84 */
} Pcc0RegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the CMP module function clock source
 *
 * This function gets the current CMP module function clock source.
 * In RUN mode, the source should be clk_core. In STOP and STANDBY mode, the source may be changed to clk_lptmr.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return CMP module function clock source
 *         - 0b : clk_core
 *         - 1b : clk_lptmr
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetCmpSrc(const Pcc0RegType *obj)
{
    return ((obj->CMP & PCC0_CMP_SRC_MASK) >> PCC0_CMP_SRC_SHIFT);
}

/*! \brief Sets the CMP module function clock source
 *
 * This function sets the CMP module function clock source.
 * In RUN mode, the source should be clk_core. In STOP and STANDBY mode, the source may be changed to clk_lptmr.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of CMP module function clock source
 *                    - 0b : clk_core
 *                    - 1b : clk_lptmr
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetCmpSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMP;

    tmp &= ~PCC0_CMP_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_CMP_SRC_SHIFT)) & PCC0_CMP_SRC_MASK);
    obj->CMP = tmp;
}

/*! \brief Gets the CMP module clock enable for both config clock and function
 *
 * This function gets the current CMP module clock enable for both config clock and function .
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return CMP module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetCmpCkEn(const Pcc0RegType *obj)
{
    return ((obj->CMP & PCC0_CMP_CKEN_MASK) >> PCC0_CMP_CKEN_SHIFT);
}

/*! \brief Sets the CMP module clock enable for both config clock and function
 *
 * This function sets the CMP module clock enable for both config clock and function .
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of CMP module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetCmpCkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMP;

    tmp &= ~PCC0_CMP_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_CMP_CKEN_SHIFT)) & PCC0_CMP_CKEN_MASK);
    obj->CMP = tmp;
}

/*! \brief Gets the CMP0 module software reset for both config clock domain and function clock domain
 *
 * This function gets the current CMP0 module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return CMP0 module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetCmpSwR(const Pcc0RegType *obj)
{
    return ((obj->CMP & PCC0_CMP_SWR_MASK) >> PCC0_CMP_SWR_SHIFT);
}

/*! \brief Sets the CMP0 module software reset for both config clock domain and function clock domain
 *
 * This function sets the CMP0 module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of CMP0 module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetCmpSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMP;

    tmp &= ~PCC0_CMP_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_CMP_SWR_SHIFT)) & PCC0_CMP_SWR_MASK);
    obj->CMP = tmp;
}

/*! \brief Gets the PORTA module clock enable for both config clock and function
 *
 * This function gets the current PORTA module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTA module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortACkEn(const Pcc0RegType *obj)
{
    return ((obj->PORTA & PCC0_PORTA_CKEN_MASK) >> PCC0_PORTA_CKEN_SHIFT);
}

/*! \brief Sets the PORTA module clock enable for both config clock and function
 *
 * This function sets the PORTA module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTA module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortACkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTA;

    tmp &= ~PCC0_PORTA_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTA_CKEN_SHIFT)) & PCC0_PORTA_CKEN_MASK);
    obj->PORTA = tmp;
}

/*! \brief Gets the PORTA module software reset for both config clock domain and function clock domain
 *
 * This function gets the current PORTA module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTA module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortASwR(const Pcc0RegType *obj)
{
    return ((obj->PORTA & PCC0_PORTA_SWR_MASK) >> PCC0_PORTA_SWR_SHIFT);
}

/*! \brief Sets the PORTA module software reset for both config clock domain and function clock domain
 *
 * This function sets the PORTA module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTA module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortASwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTA;

    tmp &= ~PCC0_PORTA_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTA_SWR_SHIFT)) & PCC0_PORTA_SWR_MASK);
    obj->PORTA = tmp;
}

/*! \brief Gets the PORTB module clock enable for both config clock and function
 *
 * This function gets the current PORTB module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTB module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortBCkEn(const Pcc0RegType *obj)
{
    return ((obj->PORTB & PCC0_PORTB_CKEN_MASK) >> PCC0_PORTB_CKEN_SHIFT);
}

/*! \brief Sets the PORTB module clock enable for both config clock and function
 *
 * This function sets the PORTB module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTB module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortBCkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTB;

    tmp &= ~PCC0_PORTB_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTB_CKEN_SHIFT)) & PCC0_PORTB_CKEN_MASK);
    obj->PORTB = tmp;
}

/*! \brief Gets the PORTB module software reset for both config clock domain and function clock domain
 *
 * This function gets the current PORTB module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTB module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortBSwR(const Pcc0RegType *obj)
{
    return ((obj->PORTB & PCC0_PORTB_SWR_MASK) >> PCC0_PORTB_SWR_SHIFT);
}

/*! \brief Sets the PORTB module software reset for both config clock domain and function clock domain
 *
 * This function sets the PORTB module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTB module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortBSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTB;

    tmp &= ~PCC0_PORTB_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTB_SWR_SHIFT)) & PCC0_PORTB_SWR_MASK);
    obj->PORTB = tmp;
}

/*! \brief Gets the PORTC module clock enable for both config clock and function
 *
 * This function gets the current PORTC module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTC module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortCCkEn(const Pcc0RegType *obj)
{
    return ((obj->PORTC & PCC0_PORTC_CKEN_MASK) >> PCC0_PORTC_CKEN_SHIFT);
}

/*! \brief Sets the PORTC module clock enable for both config clock and function
 *
 * This function sets the PORTC module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTC module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortCCkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTC;

    tmp &= ~PCC0_PORTC_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTC_CKEN_SHIFT)) & PCC0_PORTC_CKEN_MASK);
    obj->PORTC = tmp;
}

/*! \brief Gets the PORTC module software reset for both config clock domain and function clock domain
 *
 * This function gets the current PORTC module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTC module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortCSwR(const Pcc0RegType *obj)
{
    return ((obj->PORTC & PCC0_PORTC_SWR_MASK) >> PCC0_PORTC_SWR_SHIFT);
}

/*! \brief Sets the PORTC module software reset for both config clock domain and function clock domain
 *
 * This function sets the PORTC module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTC module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortCSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTC;

    tmp &= ~PCC0_PORTC_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTC_SWR_SHIFT)) & PCC0_PORTC_SWR_MASK);
    obj->PORTC = tmp;
}

/*! \brief Gets the PORTD module clock enable for both config clock and function
 *
 * This function gets the current PORTD module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTD module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortDCkEn(const Pcc0RegType *obj)
{
    return ((obj->PORTD & PCC0_PORTD_CKEN_MASK) >> PCC0_PORTD_CKEN_SHIFT);
}

/*! \brief Sets the PORTD module clock enable for both config clock and function
 *
 * This function sets the PORTD module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTD module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortDCkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTD;

    tmp &= ~PCC0_PORTD_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTD_CKEN_SHIFT)) & PCC0_PORTD_CKEN_MASK);
    obj->PORTD = tmp;
}

/*! \brief Gets the PORTD module software reset for both config clock domain and function clock domain
 *
 * This function gets the current PORTD module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTD module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortDSwR(const Pcc0RegType *obj)
{
    return ((obj->PORTD & PCC0_PORTD_SWR_MASK) >> PCC0_PORTD_SWR_SHIFT);
}

/*! \brief Sets the PORTD module software reset for both config clock domain and function clock domain
 *
 * This function sets the PORTD module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTD module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortDSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTD;

    tmp &= ~PCC0_PORTD_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTD_SWR_SHIFT)) & PCC0_PORTD_SWR_MASK);
    obj->PORTD = tmp;
}

/*! \brief Gets the PORTE module clock enable for both config clock and function
 *
 * This function gets the current PORTE module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTE module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortECkEn(const Pcc0RegType *obj)
{
    return ((obj->PORTE & PCC0_PORTE_CKEN_MASK) >> PCC0_PORTE_CKEN_SHIFT);
}

/*! \brief Sets the PORTE module clock enable for both config clock and function
 *
 * This function sets the PORTE module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTE module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortECkEn(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTE;

    tmp &= ~PCC0_PORTE_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTE_CKEN_SHIFT)) & PCC0_PORTE_CKEN_MASK);
    obj->PORTE = tmp;
}

/*! \brief Gets the PORTE module software reset for both config clock domain and function clock domain
 *
 * This function gets the current PORTE module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTE module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortESwR(const Pcc0RegType *obj)
{
    return ((obj->PORTE & PCC0_PORTE_SWR_MASK) >> PCC0_PORTE_SWR_SHIFT);
}

/*! \brief Sets the PORTE module software reset for both config clock domain and function clock domain
 *
 * This function sets the PORTE module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTE module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortESwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTE;

    tmp &= ~PCC0_PORTE_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTE_SWR_SHIFT)) & PCC0_PORTE_SWR_MASK);
    obj->PORTE = tmp;
}

/*! \brief Gets the LPTMR module function clock source
 *
 * This function gets the current LPTMR module function clock source.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPTMR module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_lpo128
 *         - 4h : clk_lpo1
 *         - 5h : clk_lpo32
 *         - 6h : RTC_CLKIN from PAD_PTA7
 *         - 7h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLptmrSrc(const Pcc0RegType *obj)
{
    return ((obj->LPTMR & PCC0_LPTMR_SRC_MASK) >> PCC0_LPTMR_SRC_SHIFT);
}

/*! \brief Sets the LPTMR module function clock source
 *
 * This function sets the LPTMR module function clock source.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPTMR module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_lpo128
 *                    - 4h : clk_lpo1
 *                    - 5h : clk_lpo32
 *                    - 6h : RTC_CLKIN from PAD_PTA7
 *                    - 7h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLptmrSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPTMR;

    tmp &= ~PCC0_LPTMR_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPTMR_SRC_SHIFT)) & PCC0_LPTMR_SRC_MASK);
    obj->LPTMR = tmp;
}

/*! \brief Gets the LPTMR module function clock divide ratio
 *
 * This function gets the current LPTMR module function clock divide ratio .
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPTMR module function clock divide ratio
 *         - 0h : 1
 *         - 1h : 2
 *         - 2h : 3
 *         - 3h : 4
 *         - 4h : 5
 *         - 5h : 6
 *         - 6h : 7
 *         - 7h : 8
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLptmrDiv(const Pcc0RegType *obj)
{
    return ((obj->LPTMR & PCC0_LPTMR_DIV_MASK) >> PCC0_LPTMR_DIV_SHIFT);
}

/*! \brief Sets the LPTMR module function clock divide ratio
 *
 * This function sets the LPTMR module function clock divide ratio .
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPTMR module function clock divide ratio
 *                    - 0h : 1
 *                    - 1h : 2
 *                    - 2h : 3
 *                    - 3h : 4
 *                    - 4h : 5
 *                    - 5h : 6
 *                    - 6h : 7
 *                    - 7h : 8
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLptmrDiv(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPTMR;

    tmp &= ~PCC0_LPTMR_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPTMR_DIV_SHIFT)) & PCC0_LPTMR_DIV_MASK);
    obj->LPTMR = tmp;
}

/*! \brief Gets the LPTMR module clock enable for both config clock and function clock
 *
 * This function gets the current LPTMR module clock enable for both config clock and function clock.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPTMR module clock enable for both config clock and function clock
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLptmrCken(const Pcc0RegType *obj)
{
    return ((obj->LPTMR & PCC0_LPTMR_CKEN_MASK) >> PCC0_LPTMR_CKEN_SHIFT);
}

/*! \brief Sets the LPTMR module clock enable for both config clock and function clock
 *
 * This function sets the LPTMR module clock enable for both config clock and function clock.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPTMR module clock enable for both config clock and function clock
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLptmrCken(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPTMR;

    tmp &= ~PCC0_LPTMR_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPTMR_CKEN_SHIFT)) & PCC0_LPTMR_CKEN_MASK);
    obj->LPTMR = tmp;
}

/*! \brief Gets the LPTMR module software reset for both config clock domain and function clock domain
 *
 * This function gets the current LPTMR module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPTMR module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLptmrSwR(const Pcc0RegType *obj)
{
    return ((obj->LPTMR & PCC0_LPTMR_SWR_MASK) >> PCC0_LPTMR_SWR_SHIFT);
}

/*! \brief Sets the LPTMR module software reset for both config clock domain and function clock domain
 *
 * This function sets the LPTMR module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPTMR module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLptmrSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPTMR;

    tmp &= ~PCC0_LPTMR_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPTMR_SWR_SHIFT)) & PCC0_LPTMR_SWR_MASK);
    obj->LPTMR = tmp;
}

/*! \brief Gets the LPIT module function clock source
 *
 * This function gets the current LPIT module function clock source.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPIT module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_pll_div
 *         - 2h : clk_sosc_div
 *         - 3h : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLpitSrc(const Pcc0RegType *obj)
{
    return ((obj->LPIT & PCC0_LPIT_SRC_MASK) >> PCC0_LPIT_SRC_SHIFT);
}

/*! \brief Sets the LPIT module function clock source
 *
 * This function sets the LPIT module function clock source.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPIT module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_pll_div
 *                    - 2h : clk_sosc_div
 *                    - 3h : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLpitSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPIT;

    tmp &= ~PCC0_LPIT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPIT_SRC_SHIFT)) & PCC0_LPIT_SRC_MASK);
    obj->LPIT = tmp;
}

/*! \brief Gets the LPIT module clock enable for both config clock and function
 *
 * This function gets the current LPIT module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPIT module clock enable for both config clock and function
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLpitCken(const Pcc0RegType *obj)
{
    return ((obj->LPIT & PCC0_LPIT_CKEN_MASK) >> PCC0_LPIT_CKEN_SHIFT);
}

/*! \brief Sets the LPIT module clock enable for both config clock and function
 *
 * This function sets the LPIT module clock enable for both config clock and function.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPIT module clock enable for both config clock and function
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLpitCken(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPIT;

    tmp &= ~PCC0_LPIT_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPIT_CKEN_SHIFT)) & PCC0_LPIT_CKEN_MASK);
    obj->LPIT = tmp;
}

/*! \brief Gets the LPIT module software reset for both config clock domain and function clock domain
 *
 * This function gets the current LPIT module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return LPIT module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLpitSwR(const Pcc0RegType *obj)
{
    return ((obj->LPIT & PCC0_LPIT_SWR_MASK) >> PCC0_LPIT_SWR_SHIFT);
}

/*! \brief Sets the LPIT module software reset for both config clock domain and function clock domain
 *
 * This function sets the LPIT module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of LPIT module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLpitSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPIT;

    tmp &= ~PCC0_LPIT_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPIT_SWR_SHIFT)) & PCC0_LPIT_SWR_MASK);
    obj->LPIT = tmp;
}

/*! \brief Gets the RTC module clock source select
 *
 * This function gets the current RTC module clock source select.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return RTC module clock source select
 *         - 0h : clk_lpo32
 *         - 1h : PAD RTC_CLKIN
 *         - 2h : lpo1
 *         - 3h : lpo1
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetRtcCntSrc(const Pcc0RegType *obj)
{
    return ((obj->RTC_CNT & PCC0_RTC_CNT_SRC_MASK) >> PCC0_RTC_CNT_SRC_SHIFT);
}

/*! \brief Sets the RTC module clock source select
 *
 * This function sets the RTC module clock source select.
 * This register should be changed after the clock is disabled at least 2 pre-changed clock cycles
 * and 2 after-changed clock cycles.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of RTC module clock source select
 *                    - 0h : clk_lpo32
 *                    - 1h : PAD RTC_CLKIN
 *                    - 2h : lpo1
 *                    - 3h : lpo1
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetRtcCntSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->RTC_CNT;

    tmp &= ~PCC0_RTC_CNT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_RTC_CNT_SRC_SHIFT)) & PCC0_RTC_CNT_SRC_MASK);
    obj->RTC_CNT = tmp;
}

/*! \brief Gets the RTC module clock enable for both config clock and function clock
 *
 * This function gets the current RTC module clock enable for both config clock and function clock.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return RTC module clock enable for both config clock and function clock
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetRtcCntCken(const Pcc0RegType *obj)
{
    return ((obj->RTC_CNT & PCC0_RTC_CNT_CKEN_MASK) >> PCC0_RTC_CNT_CKEN_SHIFT);
}

/*! \brief Sets the RTC module clock enable for both config clock and function clock
 *
 * This function sets the RTC module clock enable for both config clock and function clock.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of RTC module clock enable for both config clock and function clock
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetRtcCntCken(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->RTC_CNT;

    tmp &= ~PCC0_RTC_CNT_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_RTC_CNT_CKEN_SHIFT)) & PCC0_RTC_CNT_CKEN_MASK);
    obj->RTC_CNT = tmp;
}

/*! \brief Gets the WDG module software reset for both config clock domain and function clock domain
 *
 * This function gets the current WDG module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return WDG module software reset for both config clock domain and function clock domain
 *         - 0b : not reset
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetWdgSwR(const Pcc0RegType *obj)
{
    return ((obj->WDG & PCC0_WDG_SWR_MASK) >> PCC0_WDG_SWR_SHIFT);
}

/*! \brief Sets the WDG module software reset for both config clock domain and function clock domain
 *
 * This function sets the WDG module software reset for both config clock domain and function clock domain.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of WDG module software reset for both config clock domain and function clock domain
 *                    - 0b : not reset
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetWdgSwR(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->WDG;

    tmp &= ~PCC0_WDG_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_WDG_SWR_SHIFT)) & PCC0_WDG_SWR_MASK);
    obj->WDG = tmp;
}

/*! \brief Gets the PORTA digital filter clock source
 *
 * This function gets the current PORTA digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTA digital filter clock source
 *         - 0b : clk_apb
 *         - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortAFltSrc(const Pcc0RegType *obj)
{
    return ((obj->PORTA_FLT & PCC0_PORTA_FLT_SRC_MASK) >> PCC0_PORTA_FLT_SRC_SHIFT);
}

/*! \brief Sets the PORTA digital filter clock source
 *
 * This function sets the PORTA digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTA digital filter clock source
 *                    - 0b : clk_apb
 *                    - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortAFltSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTA_FLT;

    tmp &= ~PCC0_PORTA_FLT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTA_FLT_SRC_SHIFT)) & PCC0_PORTA_FLT_SRC_MASK);
    obj->PORTA_FLT = tmp;
}

/*! \brief Gets the PORTB digital filter clock source
 *
 * This function gets the current PORTB digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTB digital filter clock source
 *         - 0b : clk_apb
 *         - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortBFltSrc(const Pcc0RegType *obj)
{
    return ((obj->PORTB_FLT & PCC0_PORTB_FLT_SRC_MASK) >> PCC0_PORTB_FLT_SRC_SHIFT);
}

/*! \brief Sets the PORTB digital filter clock source
 *
 * This function sets the PORTB digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTB digital filter clock source
 *                    - 0b : clk_apb
 *                    - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortBFltSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTB_FLT;

    tmp &= ~PCC0_PORTB_FLT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTB_FLT_SRC_SHIFT)) & PCC0_PORTB_FLT_SRC_MASK);
    obj->PORTB_FLT = tmp;
}

/*! \brief Gets the PORTC digital filter clock source
 *
 * This function gets the current PORTC digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTC digital filter clock source
 *         - 0b : clk_apb
 *         - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortCFltSrc(const Pcc0RegType *obj)
{
    return ((obj->PORTC_FLT & PCC0_PORTC_FLT_SRC_MASK) >> PCC0_PORTC_FLT_SRC_SHIFT);
}

/*! \brief Sets the PORTC digital filter clock source
 *
 * This function sets the PORTC digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTC digital filter clock source
 *                    - 0b : clk_apb
 *                    - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortCFltSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTC_FLT;

    tmp &= ~PCC0_PORTC_FLT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTC_FLT_SRC_SHIFT)) & PCC0_PORTC_FLT_SRC_MASK);
    obj->PORTC_FLT = tmp;
}

/*! \brief Gets the PORTD digital filter clock source
 *
 * This function gets the current PORTD digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTD digital filter clock source
 *         - 0b : clk_apb
 *         - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortDFltSrc(const Pcc0RegType *obj)
{
    return ((obj->PORTD_FLT & PCC0_PORTD_FLT_SRC_MASK) >> PCC0_PORTD_FLT_SRC_SHIFT);
}

/*! \brief Sets the PORTD digital filter clock source
 *
 * This function sets the PORTD digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTD digital filter clock source
 *                    - 0b : clk_apb
 *                    - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortDFltSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTD_FLT;

    tmp &= ~PCC0_PORTD_FLT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTD_FLT_SRC_SHIFT)) & PCC0_PORTD_FLT_SRC_MASK);
    obj->PORTD_FLT = tmp;
}

/*! \brief Gets the PORTE digital filter clock source
 *
 * This function gets the current PORTE digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PORTE digital filter clock source
 *         - 0b : clk_apb
 *         - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetPortEFltSrc(const Pcc0RegType *obj)
{
    return ((obj->PORTE_FLT & PCC0_PORTE_FLT_SRC_MASK) >> PCC0_PORTE_FLT_SRC_SHIFT);
}

/*! \brief Sets the PORTE digital filter clock source
 *
 * This function sets the PORTE digital filter clock source.
 * Changing the filter clock source must be done only when all digital filters are disabled.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PORTE digital filter clock source
 *                    - 0b : clk_apb
 *                    - 1b : clk_lpo128
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetPortEFltSrc(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PORTE_FLT;

    tmp &= ~PCC0_PORTE_FLT_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_PORTE_FLT_SRC_SHIFT)) & PCC0_PORTE_FLT_SRC_MASK);
    obj->PORTE_FLT = tmp;
}

/*! \brief Gets the clk_lpo32 enable
 *
 * This function gets the current clk_lpo32 enable.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return clk_lpo32 enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLpo32Cken(const Pcc0RegType *obj)
{
    return ((obj->LPO32 & PCC0_LPO32_CKEN_MASK) >> PCC0_LPO32_CKEN_SHIFT);
}

/*! \brief Sets the clk_lpo32 enable
 *
 * This function sets the clk_lpo32 enable.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of clk_lpo32 enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLpo32Cken(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPO32;

    tmp &= ~PCC0_LPO32_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPO32_CKEN_SHIFT)) & PCC0_LPO32_CKEN_MASK);
    obj->LPO32 = tmp;
}

/*! \brief Gets the clk_lpo1 enable
 *
 * This function gets the current clk_lpo1 enable.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return clk_lpo1 enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLpo1Cken(const Pcc0RegType *obj)
{
    return ((obj->LPO1 & PCC0_LPO1_CKEN_MASK) >> PCC0_LPO1_CKEN_SHIFT);
}

/*! \brief Sets the clk_lpo1 enable
 *
 * This function sets the clk_lpo1 enable.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of clk_lpo1 enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetLpo1Cken(Pcc0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->LPO1;

    tmp &= ~PCC0_LPO1_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC0_LPO1_CKEN_SHIFT)) & PCC0_LPO1_CKEN_MASK);
    obj->LPO1 = tmp;
}

/*! \brief Sets the PCC register unlock key
 *
 * This function sets the PCC register unlock key.
 * Registers in PCC is locked by default. Before writing registers in pcc, write unlock key to this register.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \param[in] value : the value of PCC register unlock key
 *                    - 0x55534552 : unlock(USER), user key
 *                    - other : lock
 */
__attribute__((always_inline)) static inline void Pcc0Reg_SetKey(Pcc0RegType *obj, uint32_t value)
{
    obj->KEY = value;
}

/*! \brief Gets the PCC register unlock key
 *
 * This function gets the current PCC register unlock key.
 * Registers in PCC is locked by default. Before writing registers in pcc, write unlock key to this register.
 *
 * \param[in] obj : pointer to PCC0 register instance
 * \return PCC register unlock key
 *         - 0b : unlock
 *         - 1b : lock
 */
__attribute__((always_inline)) static inline uint8_t Pcc0Reg_GetLock(const Pcc0RegType *obj)
{
    return ((obj->LOCK & PCC0_LOCK_LOCK_MASK) >> PCC0_LOCK_LOCK_SHIFT);
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _PCC0_REG_H_ */
