#include   "forceSnsr_Cfg.h"
/***************************************************************
copyright from private LiuXiao
if you have any question,you can contact me by email 461445092@qq.com
2022-10-05 17:56:24.020233
***************************************************************/


forcesnsr_RxReg_un_type forcesnsr_reg_state_un;
forcesnsr_RxReg_un_type forcesnsr_reg_state_un_bak;

/*
forcesnsr main contorl stuct

all tx register default initial configration define in this table

all rx register attribute define in this table
*/

const forcesnsr_Reg_Cfg_Main_Str_typ  forcesnsr_Main_Cfg_Tbl[] = 
{
	/*tx register default initial value define  */
	{
		forcesnsr_Tx_CMD,0x00,2, (STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0]), 
		{
			0xB5,0x37, 
			forcesnsr_REG_FILL8_VAL,forcesnsr_REG_FILL6_VAL
		}
	},
	{
		forcesnsr_Tx_CMD,0x07,8,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[8]),
		{
			0x02,0x02,0x30,0x30,0x03,0x2D,0x60,0x93,
			forcesnsr_REG_FILL8_VAL
		}
	},
	{
		forcesnsr_Tx_CMD,0x16,2,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0x16]),
		{
			0x0c,0x80,
			forcesnsr_REG_FILL8_VAL,forcesnsr_REG_FILL6_VAL
		}
	},
	{
		forcesnsr_Rx_CMD,0x00,15,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0]),
		{
			forcesnsr_REG_FILL16_VAL
		}
	},
	{
		forcesnsr_Rx_CMD,0xF,9,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[15]),
		{
			forcesnsr_REG_FILL16_VAL
		}
	}
};



/***************************main function define end  ************************************/


