/*
 * Copyright (c) 2023, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _CVM012X_H_
#define _CVM012X_H_

/*! \brief Contains public interface to various functions related
 *         to all the registers of CVM012x series chips
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the Interrupt Number Definition
 ******************************************************************************/

typedef enum
{
    /* Core interrupts */
    NMI_IRQn       = -14, /**< Non Maskable Interrupt */
    HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
    SVCall_IRQn    = -5,  /**< Cortex-M0 SV Call Interrupt */
    PendSV_IRQn    = -2,  /**< Cortex-M0 Pend SV Interrupt */
    SysTick_IRQn   = -1,  /**< Cortex-M0 System Tick Interrupt */

    /* CVM012x specific interrupts */
    DMA0_IRQn              = 0u,  /**< DMA channel 0 transfer complete */
    DMA1_IRQn              = 1u,  /**< DMA channel 1 transfer complete */
    DMA2_IRQn              = 2u,  /**< DMA channel 2 transfer complete */
    DMA3_IRQn              = 3u,  /**< DMA channel 3 transfer complete */
    DMA_Error_IRQn         = 4u,  /**< DMA error interrupt channels 0-3 */
    FHU_IRQn               = 5u,  /**< FHU Interrupt, ERM single bit error correction */
    RTC_Alarm_IRQn         = 6u,  /**< RTC alarm interrupt */
    RTC_Seconds_IRQn       = 7u,  /**< RTC seconds interrupt */
    LPTMR_IRQn             = 8u,  /**< LPTIMER interrupt request */
    PORT_IRQn              = 9u,  /**< Port ABCDE pin detect interrupt */
    CAN_ORed_IRQn          = 10u, /**< CAN OR'ed [BusOff\BusOffDone\TransWarning\ReceiveWarning\..... ] */
    CAN_ORed_0_31_MB_IRQn  = 11u, /**< CAN OR'ed Message buffer (0-31) */
    CAN_ORed_32_63_MB_IRQn = 12u, /**< CAN OR'ed Message buffer (32-63) */
    MFT0_Ch0_Ch5_IRQn      = 13u, /**< MFT0 Channel 0 to 7 interrupt */
    MFT0_Fault_IRQn        = 14u, /**< MFT0 Fault interrupt */
    MFT0_Ovf_Reload_IRQn   = 15u, /**< MFT0 Counter overflow and Reload interrupt */
    MFT1_Ch0_Ch5_IRQn      = 16u, /**< MFT1 Channel 0 to 7 interrupt */
    MFT1_Fault_IRQn        = 17u, /**< MFT1 Fault interrupt */
    MFT1_Ovf_Reload_IRQn   = 18u, /**< MFT1 Counter overflow and Reload interrupt */
    FTFC_IRQn              = 19u, /**< FTFC Command done,read collision,err response interrupt */
    PDB_IRQn               = 20u, /**< PDB interrupt */
    LPIT_IRQn              = 21u, /**< LPIT interrupt */
    CMU_IRQn               = 22u, /**< CMU PLL,SOSC interrupt */
    WDOG_IRQn              = 23u, /**< Interrupt request out before wdg reset out */
    RCM_IRQn               = 24u, /**< RCM Asynchronous Interrupt, Reset interrutpt */
    I2C_IRQn               = 25u, /**< I2C Interrupt */
    SPI0_IRQn              = 26u, /**< SPI0 Interrupt */
    SPI1_IRQn              = 27u, /**< SPI1 Interrupt */
    ADC_IRQn               = 28u, /**< ADC interrupt request. */
    UART0_RxTx_IRQn        = 29u, /**< UART0 Transmit / Receive Interrupt */
    UART1_RxTx_IRQn        = 30u, /**< UART1 Transmit / Receive  Interrupt */
    TOUCH_IRQn             = 31u, /**< Touch  Interrupt */
} IRQn_Type;

/*******************************************************************************
 * the Processor and Core Peripheral Section
 ******************************************************************************/

#define __NVIC_PRIO_BITS       2 /*!< Number of Bits used for Priority Levels          */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used     */
#define __MPU_PRESENT          0 /*!< MPU present or not                               */
/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
#define __FPU_PRESENT          0 /*!< FPU present or not                                */

#define __VTOR_PRESENT         1

#include "../cmsis/core_cm0plus.h"

/*******************************************************************************
 * the Device Specific Peripheral registers structures
 ******************************************************************************/

#include "mscm_reg.h"
#include "cmu_reg.h"
#include "fhu_reg.h"
#include "edma_reg.h"
#include "crc_reg.h"
#include "mpu_reg.h"
#include "erm_reg.h"
#include "eim_reg.h"
#include "ftfc_reg.h"
#include "dmamux_reg.h"
#include "axbs_reg.h"
#include "adc_reg.h"
#include "pdb_reg.h"
#include "spi_reg.h"
#include "mft_reg.h"
#include "gpio_reg.h"
#include "flexcan_reg.h"
#include "pwmlite_reg.h"
#include "trgmux_reg.h"
#include "sim_reg.h"
#include "port_reg.h"
#include "i2c_reg.h"
#include "uart_reg.h"
#include "scg0_reg.h"
#include "scg1_reg.h"
#include "scg2_reg.h"
#include "pcc0_reg.h"
#include "pcc1_reg.h"
#include "lptmr_reg.h"
#include "lpit_reg.h"
#include "rtc_reg.h"
#include "wdg_reg.h"
#include "pmc_reg.h"
#include "rcm_reg.h"

/*******************************************************************************
 * the Peripheral memory map
 ******************************************************************************/

/* MSCM module */
#define MSCM_BASE      (0x40001000u)
#define MSCM           ((MscmRegType *)MSCM_BASE)

/* CMU module */
#define CMU_PLL_BASE   (0x40003000u)
#define CMU_PLL        ((CmuRegType *)CMU_PLL_BASE)
#define CMU_SOSC_BASE  (0x40004000u)
#define CMU_SOSC       ((CmuRegType *)CMU_SOSC_BASE)

/* FHU  module */
#define FHU_BASE       (0x40005000u)
#define FHU            ((FhuRegType *)FHU_BASE)

/* DMA module */
#define DMA_BASE       (0x40008000u)
#define DMA            ((EDmaRegType *)DMA_BASE)

/* CRC module */
#define CRC_BASE       (0x4000C000u)
#define CRC            ((CrcRegType *)CRC_BASE)

/* MPU module */
#define MPU_BASE       (0x4000D000u)
#define MPU            ((MpuRegType *)MPU_BASE)

/* ERM module */
#define ERM_BASE       (0x40018000u)
#define ERM            ((ErmRegType *)ERM_BASE)

/* EIM module */
#define EIM_BASE       (0x40019000u)
#define EIM            ((EimRegType *)EIM_BASE)

/* FTFC module */
#define FTFC_BASE      (0x40020000u)
#define FTFC           ((FtfcRegType *)FTFC_BASE)

/* DMAMUX module */
#define DMAMUX_BASE    (0x40021000u)
#define DMAMUX         ((DmamuxRegType *)DMAMUX_BASE)

/* AXBS module */
#define AXBS_BASE      (0x40022000u)
#define AXBS           ((AxbsRegType *)AXBS_BASE)

/* SPI modules */
#define SPI0_BASE      (0x4002C000u)
#define SPI0           ((SpiRegType *)SPI0_BASE)
#define SPI1_BASE      (0x4002D000u)
#define SPI1           ((SpiRegType *)SPI1_BASE)

/* MFT modules */
#define MFT0_BASE      (0x40030000u)
#define MFT0           ((MftRegType *)MFT0_BASE)
#define MFT1_BASE      (0x40031000u)
#define MFT1           ((MftRegType *)MFT1_BASE)

/* GPIO modules */
#define GPIOA_BASE     (0x40035000u)
#define GPIOA          ((GpioRegType *)GPIOA_BASE)
#define GPIOB_BASE     (0x40035040u)
#define GPIOB          ((GpioRegType *)GPIOB_BASE)
#define GPIOC_BASE     (0x40035080u)
#define GPIOC          ((GpioRegType *)GPIOC_BASE)

/* CAN modules */
#define CAN_BASE       (0x40038000u)
#define CAN            ((FlexCanRegType *)CAN_BASE)

/* PWMLITE modules */
#define PWMLITE0_BASE  (0x40058000u)
#define PWMLITE0       ((PwmLiteRegType *)PWMLITE0_BASE)
#define PWMLITE1_BASE  (0x40059000u)
#define PWMLITE1       ((PwmLiteRegType *)PWMLITE1_BASE)

/* TRGMUX module */
#define TRGMUX_BASE    (0x4005E000u)
#define TRGMUX         ((TrgMuxRegType *)TRGMUX_BASE)

/* SIM module */
#define SIM_BASE       (0x4005F000u)
#define SIM            ((SimRegType *)SIM_BASE)

/* PORT modules */
#define PORTA_BASE     (0x40060000u)
#define PORTA          ((PortRegType *)PORTA_BASE)
#define PORTB_BASE     (0x40061000u)
#define PORTB          ((PortRegType *)PORTB_BASE)
#define PORTC_BASE     (0x40062000u)
#define PORTC          ((PortRegType *)PORTC_BASE)

/* UART module */
#define UART0_BASE     (0x4006A000u)
#define UART0          ((UartRegType *)UART0_BASE)
#define UART1_BASE     (0x4006B000u)
#define UART1          ((UartRegType *)UART1_BASE)

/* SCG0 module */
#define SCG0_BASE      (0x4006E000u)
#define SCG0           ((Scg0RegType *)SCG0_BASE)
/* SCG1 module */
#define SCG1_BASE      (0x4006E400u)
#define SCG1           ((Scg1RegType *)SCG1_BASE)
/* SCG2 module */
#define SCG2_BASE      (0x4006E800u)
#define SCG2           ((Scg2RegType *)SCG2_BASE)

/* PCC0 module */
#define PCC0_BASE      (0x4006F000u)
#define PCC0           ((Pcc0RegType *)PCC0_BASE)
/* PCC1 module */
#define PCC1_BASE      (0x4006F800u)
#define PCC1           ((Pcc1RegType *)PCC1_BASE)

/* ADC modules */
#define ADC_BASE       (0x40070000u)
#define ADC            ((AdcRegType *)ADC_BASE)

/* PDB modules */
#define PDB_BASE       (0x40071000u)
#define PDB            ((PdbRegType *)PDB_BASE)

/* LPTMR module */
#define LPTMR_BASE     (0x40075000u)
#define LPTMR          ((LptmrRegType *)LPTMR_BASE)

/* LPIT module */
#define LPIT_BASE      (0x40077000u)
#define LPIT           ((LpitRegType *)LPIT_BASE)

/* RTC module */
#define RTC_BASE       (0x40078000u)
#define RTC            ((RtcRegType *)RTC_BASE)

/* WDG module */
#define WDG_BASE       (0x4007A000u)
#define WDG            ((WdgRegType *)WDG_BASE)

/* I2C modules */
#define I2C_BASE       (0x4007B000u)
#define I2C            ((I2cRegType *)I2C_BASE)

/* PMC module */
#define PMC_BASE       (0x4007D000u)
#define PMC            ((PmcRegType *)PMC_BASE)

/* RCM module */
#define RCM_BASE       (0x4007F000u)
#define RCM            ((RcmRegType *)RCM_BASE)

/* GPIO_IOP modules */
#define GPIOA_IOP_BASE (0xF8000000u)
#define GPIOA_IOP      ((GpioRegType *)GPIOA_IOP_BASE)
#define GPIOB_IOP_BASE (0xF8000040u)
#define GPIOB_IOP      ((GpioRegType *)GPIOB_IOP_BASE)
#define GPIOC_IOP_BASE (0xF8000080u)
#define GPIOC_IOP      ((GpioRegType *)GPIOC_IOP_BASE)

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _CVM012X_H_ */
