/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _SCG2_REG_H_
#define _SCG2_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the SCG2 Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* CSR Bit Fields */
#define SCG2_CSR_SYS_ST_MASK    (0x3000000u)
#define SCG2_CSR_SYS_ST_SHIFT   (24u)
#define SCG2_CSR_SYS_ST_WIDTH   (2u)
#define SCG2_CSR_SRC_SYS_MASK   (0x30000u)
#define SCG2_CSR_SRC_SYS_SHIFT  (16u)
#define SCG2_CSR_SRC_SYS_WIDTH  (2u)
#define SCG2_CSR_DIV_AIPS_MASK  (0xF00u)
#define SCG2_CSR_DIV_AIPS_SHIFT (8u)
#define SCG2_CSR_DIV_AIPS_WIDTH (4u)

/* CLKOUT Bit Fields */
#define SCG2_CLKOUT_SRC0_MASK   (0x380000u)
#define SCG2_CLKOUT_SRC0_SHIFT  (19u)
#define SCG2_CLKOUT_SRC0_WIDTH  (3u)
#define SCG2_CLKOUT_SRC1_MASK   (0x70000u)
#define SCG2_CLKOUT_SRC1_SHIFT  (16u)
#define SCG2_CLKOUT_SRC1_WIDTH  (3u)
#define SCG2_CLKOUT_DIV_MASK    (0x700u)
#define SCG2_CLKOUT_DIV_SHIFT   (8u)
#define SCG2_CLKOUT_DIV_WIDTH   (3u)
#define SCG2_CLKOUT_EN_MASK     (0x10u)
#define SCG2_CLKOUT_EN_SHIFT    (4u)
#define SCG2_CLKOUT_EN_WIDTH    (1u)

/* SIRC_MFT Bit Fields */
#define SCG2_SIRC_MFT_DIV_MASK  (0x700u)
#define SCG2_SIRC_MFT_DIV_SHIFT (8u)
#define SCG2_SIRC_MFT_DIV_WIDTH (3u)
#define SCG2_SIRC_MFT_EN_MASK   (0x10u)
#define SCG2_SIRC_MFT_EN_SHIFT  (4u)
#define SCG2_SIRC_MFT_EN_WIDTH  (1u)

/* SIRC_CFG Bit Fields */
#define SCG2_SIRC_CFG_DIV_MASK  (0x700u)
#define SCG2_SIRC_CFG_DIV_SHIFT (8u)
#define SCG2_SIRC_CFG_DIV_WIDTH (3u)
#define SCG2_SIRC_CFG_EN_MASK   (0x10u)
#define SCG2_SIRC_CFG_EN_SHIFT  (4u)
#define SCG2_SIRC_CFG_EN_WIDTH  (1u)

/* SOSC_MFT Bit Fields */
#define SCG2_SOSC_MFT_DIV_MASK  (0x700u)
#define SCG2_SOSC_MFT_DIV_SHIFT (8u)
#define SCG2_SOSC_MFT_DIV_WIDTH (3u)
#define SCG2_SOSC_MFT_EN_MASK   (0x10u)
#define SCG2_SOSC_MFT_EN_SHIFT  (4u)
#define SCG2_SOSC_MFT_EN_WIDTH  (1u)

/* SOSC_CFG Bit Fields */
#define SCG2_SOSC_CFG_DIV_MASK  (0x700u)
#define SCG2_SOSC_CFG_DIV_SHIFT (8u)
#define SCG2_SOSC_CFG_DIV_WIDTH (3u)
#define SCG2_SOSC_CFG_EN_MASK   (0x10u)
#define SCG2_SOSC_CFG_EN_SHIFT  (4u)
#define SCG2_SOSC_CFG_EN_WIDTH  (1u)

/* PLL_MFT Bit Fields */
#define SCG2_PLL_MFT_DIV_MASK   (0x700u)
#define SCG2_PLL_MFT_DIV_SHIFT  (8u)
#define SCG2_PLL_MFT_DIV_WIDTH  (3u)
#define SCG2_PLL_MFT_EN_MASK    (0x10u)
#define SCG2_PLL_MFT_EN_SHIFT   (4u)
#define SCG2_PLL_MFT_EN_WIDTH   (1u)

/* PLL_CFG Bit Fields */
#define SCG2_PLL_CFG_DIV_MASK   (0x700u)
#define SCG2_PLL_CFG_DIV_SHIFT  (8u)
#define SCG2_PLL_CFG_DIV_WIDTH  (3u)
#define SCG2_PLL_CFG_EN_MASK    (0x10u)
#define SCG2_PLL_CFG_EN_SHIFT   (4u)
#define SCG2_PLL_CFG_EN_WIDTH   (1u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of SCG2 registers
 */
typedef struct _Scg2RegType_
{
    volatile uint32_t CSR;          /*!< SYSTEM clock config register, offset: 0x0 */
    volatile uint32_t CLKOUT;       /*!< system clock out control register, offset: 0x4 */
    uint32_t          RESERVED0[2]; /*!< Reserved register, offset: 0x8 */
    volatile uint32_t SIRC_MFT;     /*!< SIRC_MFT clock div configuration register, offset: 0x10 */
    volatile uint32_t SIRC_CFG;     /*!< SIRC_DIV clock div configuration register, offset: 0x14 */
    volatile uint32_t SOSC_MFT;     /*!< SOSC_MFT clock div configuration register, offset: 0x18 */
    volatile uint32_t SOSC_CFG;     /*!< SOSC_DIV clock div configuration register, offset: 0x1C */
    volatile uint32_t PLL_MFT;      /*!< PLL_MFT clock div configuration register, offset: 0x20 */
    volatile uint32_t PLL_CFG;      /*!< PLL clock div configuration register, offset: 0x24 */
} Scg2RegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the system clock(clk_sys) source status
 *
 * This function gets the current system clock(clk_sys) source status.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return system clock(clk_sys) source status
 *         - 0h : clk_sirc
 *         - 1h : clk_sosc
 *         - 2h : clk_pll
 *         - 3h : clk_sirc
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetCsrSysSt(const Scg2RegType *obj)
{
    return ((obj->CSR & SCG2_CSR_SYS_ST_MASK) >> SCG2_CSR_SYS_ST_SHIFT);
}

/*! \brief Gets the System Clock(clk_sys) source select
 *
 * This function gets the current System Clock(clk_sys) source select.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return System Clock(clk_sys) source select
 *         - 0h : clk_sirc
 *         - 1h : clk_sosc
 *         - 2h : clk_pll
 *         - 3h : clk_sirc
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetCsrSrcSys(const Scg2RegType *obj)
{
    return ((obj->CSR & SCG2_CSR_SRC_SYS_MASK) >> SCG2_CSR_SRC_SYS_SHIFT);
}

/*! \brief Sets the System Clock(clk_sys) source select
 *
 * This function sets the System Clock(clk_sys) source select.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of System Clock(clk_sys) source select
 *                    - 0h : clk_sirc
 *                    - 1h : clk_sosc
 *                    - 2h : clk_pll
 *                    - 3h : clk_sirc
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetCsrSrcSys(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CSR;

    tmp &= ~SCG2_CSR_SRC_SYS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CSR_SRC_SYS_SHIFT)) & SCG2_CSR_SRC_SYS_MASK);
    obj->CSR = tmp;
}

/*! \brief Gets the clk_apb(APB bus Clock):Divide Ratio
 *
 * This function gets the current clk_apb(APB bus Clock):Divide Ratio.
 * The source clock is clk_core.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_apb(APB bus Clock):Divide Ratio
 *         - 0000 : Divide-by-1
 *         - 0001 : Divide-by-2
 *         - 0010 : Divide-by-3
 *         - 0011 : Divide-by-4
 *         - 0100 : Divide-by-5
 *         - 0101 : Divide-by-6
 *         - 0110 : Divide-by-7
 *         - 0111 : Divide-by-8
 *         - 1000 : Divide-by-9
 *         - 1001 : Divide-by-10
 *         - 1010 : Divide-by-11
 *         - 1011 : Divide-by-12
 *         - 1100 : Divide-by-13
 *         - 1101 : Divide-by-14
 *         - 1110 : Divide-by-15
 *         - 1111 : Divide-by-16
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetCsrDivAips(const Scg2RegType *obj)
{
    return ((obj->CSR & SCG2_CSR_DIV_AIPS_MASK) >> SCG2_CSR_DIV_AIPS_SHIFT);
}

/*! \brief Sets the clk_apb(APB bus Clock):Divide Ratio
 *
 * This function sets the clk_apb(APB bus Clock):Divide Ratio.
 * The source clock is clk_core.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_apb(APB bus Clock):Divide Ratio
 *                    - 0000 : Divide-by-1
 *                    - 0001 : Divide-by-2
 *                    - 0010 : Divide-by-3
 *                    - 0011 : Divide-by-4
 *                    - 0100 : Divide-by-5
 *                    - 0101 : Divide-by-6
 *                    - 0110 : Divide-by-7
 *                    - 0111 : Divide-by-8
 *                    - 1000 : Divide-by-9
 *                    - 1001 : Divide-by-10
 *                    - 1010 : Divide-by-11
 *                    - 1011 : Divide-by-12
 *                    - 1100 : Divide-by-13
 *                    - 1101 : Divide-by-14
 *                    - 1110 : Divide-by-15
 *                    - 1111 : Divide-by-16
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetCsrDivAips(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CSR;

    tmp &= ~SCG2_CSR_DIV_AIPS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CSR_DIV_AIPS_SHIFT)) & SCG2_CSR_DIV_AIPS_MASK);
    obj->CSR = tmp;
}

/*! \brief Gets the scg clock out
 *
 * This function gets the current scg clock out.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return scg clock out
 *         - 0b : clk_cnt_fls
 *         - 1b : clk_sosc
 *         - 2h : clk_sirc
 *         - 3h : clk_pll
 *         - 4h : clk_core
 *         - 5h : clk_apb
 *         - 6h : clk_sosc_div
 *         - 7h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetClkOutSrc0(const Scg2RegType *obj)
{
    return ((obj->CLKOUT & SCG2_CLKOUT_SRC0_MASK) >> SCG2_CLKOUT_SRC0_SHIFT);
}

/*! \brief Sets the scg clock out
 *
 * This function sets the scg clock out.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of scg clock out
 *                    - 0b : clk_cnt_fls
 *                    - 1b : clk_sosc
 *                    - 2h : clk_sirc
 *                    - 3h : clk_pll
 *                    - 4h : clk_core
 *                    - 5h : clk_apb
 *                    - 6h : clk_sosc_div
 *                    - 7h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetClkOutSrc0(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CLKOUT;

    tmp &= ~SCG2_CLKOUT_SRC0_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CLKOUT_SRC0_SHIFT)) & SCG2_CLKOUT_SRC0_MASK);
    obj->CLKOUT = tmp;
}

/*! \brief Gets the clock out(to PAD) source
 *
 * This function gets the current clock out(to PAD) source.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clock out(to PAD) source
 *         - 0b : scg_out
 *         - 1h : clk_pll_div
 *         - 2h : clk_lpo128
 *         - 3h : clk_lpo32
 *         - 4h : clk_lpo1
 *         - 5h : clk_rtc_cnt
 *         - 6h : clk_sirc
 *         - 7h : clk_sirc
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetClkOutSrc1(const Scg2RegType *obj)
{
    return ((obj->CLKOUT & SCG2_CLKOUT_SRC1_MASK) >> SCG2_CLKOUT_SRC1_SHIFT);
}

/*! \brief Sets the clock out(to PAD) source
 *
 * This function sets the clock out(to PAD) source.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clock out(to PAD) source
 *                    - 0b : scg_out
 *                    - 1h : clk_pll_div2
 *                    - 2h : clk_lpo128
 *                    - 3h : clk_lpo32
 *                    - 4h : clk_lpo1
 *                    - 5h : clk_rtc_cnt
 *                    - 6h : clk_sirc
 *                    - 7h : clk_sirc
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetClkOutSrc1(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CLKOUT;

    tmp &= ~SCG2_CLKOUT_SRC1_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CLKOUT_SRC1_SHIFT)) & SCG2_CLKOUT_SRC1_MASK);
    obj->CLKOUT = tmp;
}

/*! \brief Gets the clock out divide ratio
 *
 * This function gets the current clock out divide ratio.
 *
 * \note The max frequency is 24M, so this bit should be configured properly.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clock out divide ratio
 *         - 0b : 1
 *         - 1b : 2
 *         - 2h : 3
 *         - 3h : 4
 *         - 4h : 5
 *         - 5h : 6
 *         - 6h : 7
 *         - 7h : 8
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetClkOutDiv(const Scg2RegType *obj)
{
    return ((obj->CLKOUT & SCG2_CLKOUT_DIV_MASK) >> SCG2_CLKOUT_DIV_SHIFT);
}

/*! \brief Sets the clock out divide ratio
 *
 * This function sets the clock out divide ratio.
 *
 * \note The max frequency is 24M, so this bit should be configured properly.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clock out divide ratio
 *                    - 0b : 1
 *                    - 1b : 2
 *                    - 2h : 3
 *                    - 3h : 4
 *                    - 4h : 5
 *                    - 5h : 6
 *                    - 6h : 7
 *                    - 7h : 8
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetClkOutDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CLKOUT;

    tmp &= ~SCG2_CLKOUT_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CLKOUT_DIV_SHIFT)) & SCG2_CLKOUT_DIV_MASK);
    obj->CLKOUT = tmp;
}

/*! \brief Gets the clock out enable
 *
 * This function gets the current clock out enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clock out enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetClkOutEn(const Scg2RegType *obj)
{
    return ((obj->CLKOUT & SCG2_CLKOUT_EN_MASK) >> SCG2_CLKOUT_EN_SHIFT);
}

/*! \brief Sets the clock out enable
 *
 * This function sets the clock out enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clock out enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetClkOutEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CLKOUT;

    tmp &= ~SCG2_CLKOUT_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_CLKOUT_EN_SHIFT)) & SCG2_CLKOUT_EN_MASK);
    obj->CLKOUT = tmp;
}

/*! \brief Gets the SIRC_DIV_MFT clock diviation
 *
 * This function gets the current SIRC_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return SIRC_DIV_MFT clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSircMftDiv(const Scg2RegType *obj)
{
    return ((obj->SIRC_MFT & SCG2_SIRC_MFT_DIV_MASK) >> SCG2_SIRC_MFT_DIV_SHIFT);
}

/*! \brief Sets the SIRC_DIV_MFT clock diviation
 *
 * This function sets the SIRC_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of SIRC_DIV_MFT clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSircMftDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SIRC_MFT;

    tmp &= ~SCG2_SIRC_MFT_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SIRC_MFT_DIV_SHIFT)) & SCG2_SIRC_MFT_DIV_MASK);
    obj->SIRC_MFT = tmp;
}

/*! \brief Gets the clk_sirc_div_mft clock enable
 *
 * This function gets the current clk_sirc_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_sirc_div_mft clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSircMftEn(const Scg2RegType *obj)
{
    return ((obj->SIRC_MFT & SCG2_SIRC_MFT_EN_MASK) >> SCG2_SIRC_MFT_EN_SHIFT);
}

/*! \brief Sets the clk_sirc_div_mft clock enable
 *
 * This function sets the clk_sirc_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_sirc_div_mft clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSircMftEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SIRC_MFT;

    tmp &= ~SCG2_SIRC_MFT_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SIRC_MFT_EN_SHIFT)) & SCG2_SIRC_MFT_EN_MASK);
    obj->SIRC_MFT = tmp;
}

/*! \brief Gets the SIRC_DIV clock diviation
 *
 * This function gets the current SIRC_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return SIRC_DIV clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSircCfgDiv(const Scg2RegType *obj)
{
    return ((obj->SIRC_CFG & SCG2_SIRC_CFG_DIV_MASK) >> SCG2_SIRC_CFG_DIV_SHIFT);
}

/*! \brief Sets the SIRC_DIV clock diviation
 *
 * This function sets the SIRC_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of SIRC_DIV clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSircCfgDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SIRC_CFG;

    tmp &= ~SCG2_SIRC_CFG_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SIRC_CFG_DIV_SHIFT)) & SCG2_SIRC_CFG_DIV_MASK);
    obj->SIRC_CFG = tmp;
}

/*! \brief Gets the clk_sirc_div clock enable
 *
 * This function gets the current clk_sirc_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_sirc_div clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSircCfgEn(const Scg2RegType *obj)
{
    return ((obj->SIRC_CFG & SCG2_SIRC_CFG_EN_MASK) >> SCG2_SIRC_CFG_EN_SHIFT);
}

/*! \brief Sets the clk_sirc_div clock enable
 *
 * This function sets the clk_sirc_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_sirc_div clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSircCfgEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SIRC_CFG;

    tmp &= ~SCG2_SIRC_CFG_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SIRC_CFG_EN_SHIFT)) & SCG2_SIRC_CFG_EN_MASK);
    obj->SIRC_CFG = tmp;
}

/*! \brief Gets the SOSC_DIV_MFT clock diviation
 *
 * This function gets the current SOSC_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return SOSC_DIV_MFT clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSoscMftDiv(const Scg2RegType *obj)
{
    return ((obj->SOSC_MFT & SCG2_SOSC_MFT_DIV_MASK) >> SCG2_SOSC_MFT_DIV_SHIFT);
}

/*! \brief Sets the SOSC_DIV_MFT clock diviation
 *
 * This function sets the SOSC_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of SOSC_DIV_MFT clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSoscMftDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SOSC_MFT;

    tmp &= ~SCG2_SOSC_MFT_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SOSC_MFT_DIV_SHIFT)) & SCG2_SOSC_MFT_DIV_MASK);
    obj->SOSC_MFT = tmp;
}

/*! \brief Gets the clk_sosc_div_mft clock enable
 *
 * This function gets the current clk_sosc_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_sosc_div_mft clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSoscMftEn(const Scg2RegType *obj)
{
    return ((obj->SOSC_MFT & SCG2_SOSC_MFT_EN_MASK) >> SCG2_SOSC_MFT_EN_SHIFT);
}

/*! \brief Sets the clk_sosc_div_mft clock enable
 *
 * This function sets the clk_sosc_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_sosc_div_mft clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSoscMftEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SOSC_MFT;

    tmp &= ~SCG2_SOSC_MFT_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SOSC_MFT_EN_SHIFT)) & SCG2_SOSC_MFT_EN_MASK);
    obj->SOSC_MFT = tmp;
}

/*! \brief Gets the SOSC_DIV clock diviation
 *
 * This function gets the current SOSC_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return SOSC_DIV clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSoscCfgDiv(const Scg2RegType *obj)
{
    return ((obj->SOSC_CFG & SCG2_SOSC_CFG_DIV_MASK) >> SCG2_SOSC_CFG_DIV_SHIFT);
}

/*! \brief Sets the SOSC_DIV clock diviation
 *
 * This function sets the SOSC_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of SOSC_DIV clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSoscCfgDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SOSC_CFG;

    tmp &= ~SCG2_SOSC_CFG_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SOSC_CFG_DIV_SHIFT)) & SCG2_SOSC_CFG_DIV_MASK);
    obj->SOSC_CFG = tmp;
}

/*! \brief Gets the clk_sosc_div clock enable
 *
 * This function gets the current clk_sosc_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_sosc_div clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetSoscCfgEn(const Scg2RegType *obj)
{
    return ((obj->SOSC_CFG & SCG2_SOSC_CFG_EN_MASK) >> SCG2_SOSC_CFG_EN_SHIFT);
}

/*! \brief Sets the clk_sosc_div clock enable
 *
 * This function sets the clk_sosc_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_sosc_div clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetSoscCfgEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SOSC_CFG;

    tmp &= ~SCG2_SOSC_CFG_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_SOSC_CFG_EN_SHIFT)) & SCG2_SOSC_CFG_EN_MASK);
    obj->SOSC_CFG = tmp;
}

/*! \brief Gets the PLL_DIV_MFT clock diviation
 *
 * This function gets the current PLL_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return PLL_DIV_MFT clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /(128)
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetPllMftDiv(const Scg2RegType *obj)
{
    return ((obj->PLL_MFT & SCG2_PLL_MFT_DIV_MASK) >> SCG2_PLL_MFT_DIV_SHIFT);
}

/*! \brief Sets the PLL_DIV_MFT clock diviation
 *
 * This function sets the PLL_DIV_MFT clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of PLL_DIV_MFT clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /(128)
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetPllMftDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_MFT;

    tmp &= ~SCG2_PLL_MFT_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_PLL_MFT_DIV_SHIFT)) & SCG2_PLL_MFT_DIV_MASK);
    obj->PLL_MFT = tmp;
}

/*! \brief Gets the clk_pll_div_mft clock enable
 *
 * This function gets the current clk_pll_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_pll_div_mft clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetPllMftEn(const Scg2RegType *obj)
{
    return ((obj->PLL_MFT & SCG2_PLL_MFT_EN_MASK) >> SCG2_PLL_MFT_EN_SHIFT);
}

/*! \brief Sets the clk_pll_div_mft clock enable
 *
 * This function sets the clk_pll_div_mft clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_pll_div_mft clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetPllMftEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_MFT;

    tmp &= ~SCG2_PLL_MFT_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_PLL_MFT_EN_SHIFT)) & SCG2_PLL_MFT_EN_MASK);
    obj->PLL_MFT = tmp;
}

/*! \brief Gets the PLL_DIV clock diviation
 *
 * This function gets the current PLL_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return PLL_DIV clock diviation
 *         - 0b : Divide by 1
 *         - 1b : Divide by 2
 *         - 2h : Divide by 4
 *         - 3h : Divide by 8
 *         - 4h : Divide by 16
 *         - 5h : Divide by 32
 *         - 6h : Divide by 64
 *         - 7h : /(128)
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetPllCfgDiv(const Scg2RegType *obj)
{
    return ((obj->PLL_CFG & SCG2_PLL_CFG_DIV_MASK) >> SCG2_PLL_CFG_DIV_SHIFT);
}

/*! \brief Sets the PLL_DIV clock diviation
 *
 * This function sets the PLL_DIV clock diviation.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of PLL_DIV clock diviation
 *                    - 0b : Divide by 1
 *                    - 1b : Divide by 2
 *                    - 2h : Divide by 4
 *                    - 3h : Divide by 8
 *                    - 4h : Divide by 16
 *                    - 5h : Divide by 32
 *                    - 6h : Divide by 64
 *                    - 7h : /(128)
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetPllCfgDiv(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CFG;

    tmp &= ~SCG2_PLL_CFG_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_PLL_CFG_DIV_SHIFT)) & SCG2_PLL_CFG_DIV_MASK);
    obj->PLL_CFG = tmp;
}

/*! \brief Gets the clk_pll_div clock enable
 *
 * This function gets the current clk_pll_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \return clk_pll_div clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Scg2Reg_GetPllCfgEn(const Scg2RegType *obj)
{
    return ((obj->PLL_CFG & SCG2_PLL_CFG_EN_MASK) >> SCG2_PLL_CFG_EN_SHIFT);
}

/*! \brief Sets the clk_pll_div clock enable
 *
 * This function sets the clk_pll_div clock enable.
 *
 * \param[in] obj : pointer to SCG2 register instance
 * \param[in] value : the value of clk_pll_div clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Scg2Reg_SetPllCfgEn(Scg2RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CFG;

    tmp &= ~SCG2_PLL_CFG_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG2_PLL_CFG_EN_SHIFT)) & SCG2_PLL_CFG_EN_MASK);
    obj->PLL_CFG = tmp;
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _SCG2_REG_H_ */
